Cypress Semiconductor /psoc63 /SCB0 /CMD_RESP_STATUS

I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address).

The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).

This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is ‘0’, the field is reliable.

I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address).

The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).

This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is ‘0’, the field is reliable.

Indicates whether there is an ongoing bus transfer to the IP. ‘0’: no ongoing bus transfer. ‘1’: ongoing bus transfer.

For SPI, the field is ‘1’ when slave mode is selected.

For I2C, the field is set to ‘1’ at a I2C START/RESTART. In case of an address match, the field is set to ‘0’ on a I2C STOP. In case of NO address match, the field is set to ‘0’ after the failing address match.

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